1. Field of the Invention
The invention relates to memories, and more particularly to flash memories.
2. Description of the Related Art
Referring to FIG. 1, a schematic diagram of transmission timings of a write command from a host to a data storage device is shown. Assume that the data storage device comprises a flash memory for data storage. When a host wants to write data to the data storage device, the host first sends a first portion write command with an identifier 0x80 to the data storage device. The host then sequentially sends column address and row address to the data storage device to indicate the address for storing data. The host then transmits the data to be stored in the data storage device, and then sends a second portion write command with an identifier 0x10 to the data storage device. After transmission of the second portion write command is completed, a voltage of a ready/busy line coupled between the host and the data storage device is lowered by the data storage device, thereby preventing the host from sending subsequent write commands or data. According to a protocol specification, a processing time period Tprog for lowering the voltage of the ready/busy line cannot be longer than 250 ms. During the processing time period Tprog, the data storage device writes the received data to a flash memory according to the row address and the column address. After data writing is completed, the data storage device then raises the voltage of the ready/busy line, so that the host can then send a read status command to the data storage device to inquire about the execution status of a previous write command.
A flash memory comprises a plurality of blocks, and each block comprises a plurality of pages for data storage. A page can be programmed to store data. When a page has stored data, the page cannot be written to again. After data of a block comprising the page is erased, the page can be programmed again to store data again. When a data storage device executes a write command, if a page with an address corresponding to the write command has already stored original data, the data storage device cannot directly write updated data to the page. Instead, the data storage device would write the updated data to a page of a spare block, and then build a mapping relationship between the spare block and a block containing the page storing the original data. The block containing the page storing the original data is referred to as a mother block, the spare block storing the updated data is referred to as a child block, and the mother block and the child block correspond to the same logical address are referred to as a block pair.
Ordinarily, to maintain a block pair, a controller must record information of the block pair. When a total number of block pairs in a flash memory increases, data amount of the recorded information also increases. To reduce memory space occupied by the recorded information of the block pairs, the controller must keep the total number of block pairs lower then a threshold value. Ordinarily, a data storage device can write received data of a write command to a flash memory during the processing time period Tprog. When a new block pair is needed to be built due to execution of a write command, in efforts to keep the total number of block pairs constant, the controller must integrate a block pair selected from existing block pairs to reduce the total number of block pairs before the write command is executed.
Because a mother block and a child block of the selected block pair comprise a plurality of pages, integration of the selected block pair requires a long time period, which is longer than the length 250 ms of the interval Tprog between the reception of the write command and a subsequent write command. When the flash memory is a multi-level-cell (MLC) flash memory or a triple-level-cell (TLC) flash memory, a mother block and a child block must store great amounts of data; thereby increasing the time period for integrating the mother block and the child block. If integration of the selected block pair cannot be completed during the time interval Tprog between reception of the write command and a subsequent write command, error may occur when the write command is executed; thus degrading the performance of the data storage device. A data writing method for solving the aforementioned problem is therefore required.